1. Field of the Invention
The present invention relates to nonvolatile memory devices, including flash memory and page mode flash memory, which include program and program verify operations.
2. Description of Related Art
Nonvolatile memory devices typically include a memory array comprising memory cells that maintain their data even when electrical power has been removed from the device. There are a variety of types of nonvolatile memory devices. One type includes so-called “read only memory,” like mask ROM in which the data is stored in the memory cell by implanting impurities in the channel region of MOS transistors. The data stored in mask ROM devices, and other nonvolatile read only memory devices, cannot be changed in the field. Another type of nonvolatile memory device includes electrically erasable and programmable memory cells, such as flash memory. The data stored in flash memory cells, and other nonvolatile electrically erasable and programmable memory cells, can be changed in the field using electronic programming and erasing procedures. Representative flash memory technologies include floating gate memory cells and charge trapping memory cells such as SONOS, NROM, PHINES and the like.
There are a variety of biasing procedures that are used for programming and erasing memory cells in flash memory. The biasing procedures for floating gate memory cells and charge trapping memory cells cause tunneling of electrons and/or holes into and out of the floating gates or charge trapping structures. The concentration of charge held in the floating gates or the charge trapping structures has an effect on the threshold voltage of the memory cell. Thus, by controlling the amount of charge held in the floating gates or in the charge trapping structures, the threshold voltage of the memory cell can be set, and data stored.
Due to demand for faster access times combined with large, high-density arrays for flash memory, page read and burst read flash memories have been developed. In normal flash memory, the read operation is executed word by word so that within a specified time, such as time after address transition (TAA of for example 100 ns to 70 ns or less) or time after a chip enable signal (TCE), only one 16-bit word is addressed, its contents sensed, and its data output. In page mode devices, the input and output structures for the array may include a fast access buffer storing a page including for example, 1024 bits or 2048 bits, on the chip. The programming and reading procedures use the page buffer to improve throughput, and in some cases are set up to provide for addressing more than one word at a time, such as four words (64 bits) or more, during programming to and reading from the page buffer. Data stored in the page buffer can be read out in burst mode or otherwise with very short cycle times.
According to a typical process, to program a page in the array, a page buffer is loaded with data to be programmed, which is then transferred in chunks to bit latches associated with a set of sense amplifiers, including for example 32 or 64 coupled via decoding circuits to columns in the array, and programming the chunks of the page in parallel, with the program bias for each bit line being controlled by the data in the corresponding bit latch. A verify procedure for page mode programming can include automatically clearing the bits in the page buffer which correspond to cells that are successfully programmed. The data stored in the page buffer is then read to confirm that all bits have been cleared to indicate a successful page program operation.
As mentioned above, the operation to program the cells in a flash memory device typically involves a procedure that causes injection or ejection of charge into a charge storage structure that affects the threshold of the cell. The charge injection or ejection procedure must be tightly controlled for modern, high density operations. For multiple bit per cell embodiments, even greater control of the charge injection or ejection operation is required.
Because of the need for precise control of cell thresholds in memory devices along with variations in memory cell characteristics, variations in voltages applied, and variations in other parameters across an array, the biasing procedures used for programming and erasing operations in flash memory can result in non-uniform levels of charge stored in the cells distributed across the array. Therefore, the biasing procedures applied in many devices include a sequence of programming with verify operations between each pulse, or between each set of pulses. A typical verify process includes driving word line voltages to program verify levels, which are changed slightly from the standard read level in order to provide program or erase margin. Then, data is sensed from the memory cells to determine whether each cell has been successfully programmed or erased. If the verify process fails, then retry program pulses followed by verify operations, are applied iteratively until a successful verify is achieved, or a maximum number of retries is reached.
For precise control of the threshold, memory devices are designed so that several iterations of the program and verify procedure may be required, that cause small increments in change of the threshold voltages for convergence on a target threshold level in a given cell on the device. The time required for a program operation therefore includes a plurality of cycles including both the program pulse and the program verify interval. See, U.S. Pat. No. 6,714,457 by Hsu et al.; U.S. Pat. No. 5,835,414 by Hung et al.; U.S. Pat. No. 5,748,535 by Takahashi et al.; U.S. Pat. No. 5,751,637 by Hung et al.; U.S. Pat. No. 5,787,039 by Liu et al.; U.S. Pat. No. 5,638,326 by Hollmer; and U.S. Pat. No. 6,141,253 by Lin.
It is desirable to provide an architecture for nonvolatile memory and program and program verify procedures for such memory, that reduces the time required for the program operation while supporting precise control over memory cell threshold voltages.